This invention relates to a computer system having a central processing unit which includes a cache memory unit, and more particularly, to an apparatus which forces a read from a main memory when an error is detected during a read from the cache memory.
In the art relating to computer systems, a significant limiting factor in the performance of large computers is the access time of a central processor unit (CPU) to a main memory. The access time to the main memory in such computer systems is due in large part to arbitration, bus, and controller delays in the memory access path. On the other hand, high speed random access memories (RAMs) provide a memory with a much faster access time. The effective access time of the memory of a large computer system may be improved, while the main memory continues to be of the relatively slow access type, by the addition of a smaller random access memory that is located close to and used exclusively by the CPU. That small random access memory generally has a faster access time than the main memory and is referred to in the art as a cache memory.
The conventional structure of a cache includes a content addressable memory and a data memory. The content addressable memory is used to relate the address supplied by the processor with a location in the data memory containing the value of the word. When the CPU makes a memory request, the address is presented to the content addressable memory, also referred to herein as a directory. If the content of that address is present in the cache, a "hit" occurs indicating that this data is available and can be fetched from cache. If the content addressable memory does not indicate that the requested address is present, a "miss" occurs and the data must then be fetched from the main memory in the usual way. As the data is read from the main memory, it is also loaded into the cache and the corresponding content addressable memory updated.
Generally, reads from memory including main memory or cache memory utilize some form of checking in order to verify the data is error free; namely, parity checking. If a parity error is detected in a store-into system, the present day systems generate an error signal and abort the system because there is no way to recover, i.e., the data in the cache is the only up to date copy since the data is stored in cache until the data has to be transferred into main memory (swapped out). If a parity error is detected in a store-thru system, the present day systems generate an error signal and abort although the data is correct and available in main memory.
In the computer system which utilizes the present invention, data is stored into both cache and main memory (which is also known as a store-through approach). Therefore, when there is a parity error detected on the information read from the directory or from the cache memory, the apparatus of the present invention forces a "miss" result thereby causing the CPU to refetch the data from main memory.
In the system which utilizes the present invention, parity checking is utilized rather than error detection and correction (EDAC). The time required to do the parity checking versus error detecting and correcting is substantially less such that a substantial time advantage is achieved. Because of the high reliability of today's components, the number of times a refetch is performed is relatively low. Further, the preferred embodiment of the system which utilizes the present invention fetches the information from the directory and the cache memory in parallel. These combined factors favor parity checking to yield the optimum time advantage without affecting system operation or system reliability.